In the document “A dual gate emitter switched thyristor (DTG-EST) with dual trench gate electrode and different gate oxide thickness” by D. Kim et al, Microelectronic Engineering 70 (2003), pp. 50-57, a conventional emitter switched thyristor (EST) with a trench gate structure is described. With reference to FIG. 1, this EST is a bipolar power semiconductor device 1′ which includes an emitter electrode 11 on an emitter side 12 of a wafer, and a collector electrode 15 on a collector side 16 of the wafer. The collector side 16 lies opposite to the emitter side 12 on the wafer. The EST includes an n-doped source region 3 and a p-doped base layer on the emitter side 12. The trench gate electrode 2 is arranged in the same plane as the base layer 4 and it is electrically insulated from the source region 3 and the base layer 4 by an insulation layer 25. An n-doped enhancement layer 5, a p-doped well layer 6 and a drift layer 7 are arranged in succession on the base layer 4. A p-doped collector layer 8 is arranged on the drift layer 7 towards the collector side 16 and contacts the collector electrode 15.
The layers are arranged in planes parallel to the emitter side 12 and each layer includes a bottom, which is the maximum distance to which the layer extends from the emitter side 12. The p-doped well layer 6 includes a well layer bottom 611, which is closer to the emitter side 12 than the gate bottom 211.
The n-doped enhancement layer 5 is floating, whereas the base layer 4 and the well layer 6 are connected in a third dimension and thereby shorted.
The EST has a turn-on MOSFET between the enhancement layer 5, the well layer 6 and the drift layer 7. A turn-off MOSFET is formed between the source region 3, the base layer 4 and the floating enhancement layer 5.
The trench EST designs as shown in FIG. 1 are based on introducing an n-type enhancement layer 5 at the MOS cell to allow a thyristor operation with a lowest possible on-state voltage drop. I In this case, the enhancement layer acts as a floating n-type emitter layer with doping up to and exceeding 1018 cm-3. Weaker doping of the enhancement layer causes the trench EST to operate in its IGBT mode characterized by an increase of the on-state voltage and the gradual emergence of collector current saturation. In this design case, the enhancement layer acts to improve the carrier spreading and to increase the PIN effect. To obtain current saturation in a trench EST up to high collector-emitter voltages and a large safe operating area (SOA), the doping of the enhancement layer must be limited to levels close to 1016 cm-3. However, this limits the trench EST performance at a level comparable to conventional trench insulated gate bipolar transistors (IGBTs) employing n-type enhancement layers. In a trench IGBT, the enhancement layer 5 introduces a peak electric field near the junction thus limiting the avalanche capability of the device.